1. Field of the Invention
This invention relates generally to switch mode power converters, and more particularly to control schemes for operating a switch mode power converter with a full bridge with synchronous rectifiers topology.
2. Description of the Related Art
A power converter with a full bridge with synchronous rectifiers (SR) topology is shown in FIG. 1a. Such converters are often used in high power applications such as telecom, networking, servers, etc., in which the converter receives a DC input voltage typically in the range of 36-72 volts. In the exemplary embodiment shown, four transistors Q1-Q4 are arranged in a full bridge configuration, with the bridge's input connected across a DC input voltage Vin and its output—taken at circuit nodes A and B—connected across the primary winding of a transformer T. First and second synchronous rectifiers SR1 and SR2 are coupled between the secondary side of transformer T and an output circuit, which includes an output inductor Lo and capacitor Co and which provides an output voltage Vo suitable for driving a load Ro. Q1-Q4 and SR1 and SR2 are typically implemented with MOSFETs, though other devices might also be used.
Normal operation of the full bridge converter is illustrated in FIG. 1b. Transistors Q1, Q4 and Q2, Q3 are alternately turned on and off to apply an AC voltage (VAB) across the primary side of transformer T. SR1 and SR2 are also turned on and off alternately to control the current IL in inductor Lo. When operated in continuous conduction mode (CCM), SR1 and SR2 periodically overlap, such as between times t2 and t3; this has the effect of shorting the secondary winding, and thereby forcing VAB to zero.
A full bridge converter of this sort has associated “dead time” (Tdt) values, defined as follows: 1) the time between the falling edge of SR2 and the rising edge of Q1,Q4 (Tdt1); 2) time between the falling edge of SR1 and the rising edge of Q2,Q3 (Tdt2); 3) the time the falling edge of Q1,Q4 and the rising edge of SR2 (Tdt3); and 4) the time between the edge of Q2,Q3 and the rising edge of SR1 (Tdt4). To achieve the highest efficiency at full the converter is typically arranged to have a short, fixed dead time. However, a light load the rate of change for primary side voltage VAB, such that a short dead time can result in VAB being shorted by SR1 and SR2 or prematurely forced to ±Vin before it reaches zero or Vin normally. This would induce a large current in the circuitry, which causes power loss and loss of efficiency at light loads. This may be unacceptable when there is a requirement that a supply meet a certain efficiency specification all across its load range, rather than just at a single load point.